IBM

TSMC’s First Breakthrough: The Copper/Low-K Interconnect

TSMC’s First Breakthrough: The Copper/Low-K Interconnect Transition

#TSMCs #Breakthrough #CopperLowK #Interconnect

“Asianometry”

Links: – The Asianometry Newsletter: – Patreon: – Threads: …

source

 

To see the full content, share this page by clicking one of the buttons below

Related Articles

28 Comments

  1. I wonder how much state sponsorship and national prestige would have helped American companies remain at the top. Clearly, TSMC folks felt the love from the “silicon island” national strategy.

  2. There is a lot of bad information in this video. I'm not saying it's all bad but there is enough that I stopped at 16:00 because I knew the presenter did not know the subject matter.

  3. I remember the introduction of copper interconnect. At the company where I worked, there was concern about the reactivity of Cu with Si02 and the difficulties posed by the barrier metals at that time – titanium and I think palladium and tungsten, which were all causing problems because they were such hard metals. But that speed pickup from Cu was irresistible. That's also when companies and foundries started to get very interested in better insulators/IMDs like 'Coral.'
    Interesting that tantalum became the barrier metal of choice.

  4. One of the reasons that Motorola matched IBM in bringing Coppers interconnects to production was that the IPAM (Intellectual Property Asset Management) group at Motorola could assess the different technologies and processes that IBM was asking to include in the cross-licensing and patent portfolio reconciliations between Motorola and IBM. The requests at the time all pointed at Copper. Since Motorola and IBM dwarfed all other US patent portfolios, they performed regular reconciliation in the licensing agreements, and the communications between the two were ongoing, formalized and professional.
    The Motorola Physical Science Research Lab in Tempe was investigating Copper at the same time, and they were referencing those same techniques, so it confirmed to the Motorola SPS (Semiconductor Product Sector) that they were on the same (right) track. Motorola SPS was engaged with AMD in Austin on Copper as well, and the SOI process that they both used came from cross-licensing with IBM.
    Since IBM had already decided to go into Financial Engineering in preference to building actually desirable products, both AMD and Motorola knew that they could be able to develop and execute on Copper without much issue from IBM, and that Intel would stay on the High-K Metal Gate Train because they had capacity to protect and Marketing Development Funds to spend to keep their customers happy with old chips.

  5. It makes me wonder why they just didn't LeapFrog to Silver. Oh that's right the CEOs of the companies made this decision so they would have somewhere to go to later. Let's keep the upgrades going on a gradual pace . 😉

  6. There is a major point that this article miss out. The choice of copper to replace aluminium is not due to better conductivity, ( The two materials do not differ too much), but a phenomenon called electromigration. When the conduction lines get thinner, and substantial current passes through, aluminium material moves in the direction of the electrons and finally the wires break. Copper behaves much better than aluminium in this aspect.

  7. Thanks for the video. I was with AMD that time, and we had a good cooperation with Motorola for the copper process. I remember having at the begin a real grazy separation in FEOL and BEOL, production areas ,later it came clear it didn’t need to be that harsh.

  8. How old is this video? Dual-Damascene process with copper interconnects is over a decade old. Low K dielectric is used to reduce capacitance for faster chip.

  9. Lol, reference to kowloon wall city , i visited that place in the mid 80s , it was near main airport Kai Tak , i walked around the kowloon city and saw that monster overcrowded building , it was something else.

  10. 10-15 metal layers is outdated already (lol) – there's actual documentation about how many metal layers the Intel 7 and Intel 4 processes include, for example. Depending on if you include the 'giant metal' layers, it's either 15/16 or 17/18 for Intel 7/4 respectively.
    I doubt AMD, Nvidia or Apple's current offerings are less complex than those by intel.

  11. It is unfortunate that most topological superconducting materials dont play well with common etch processes. Materials like BiSnTe2 or graphene. They exhibit surface superconductivity in namometer thick layer but are resistant to most etching chemicals or form insoluble chemicals.

  12. Small correction at 17:40 . This is an edge bead removal chamber used to etch away copper seed on the edge post electroplating. You can see a small grey arm used to dispense etchant on the edge of the plated wafer. Great video, love your content!

  13. Polite Correction: Many memory layers, Many more than you suggest. Very many. Currently Yanggtse is the leader.
    And, regarding my previous comment about latency, a good future subject is how the off die memory latency problem has been solved. Might need multiple videos. More copper too!

Leave a Reply